FIELD OF THE INVENTION
The invention relates to a monolithically integrated semiconductor circuit apparatus having a semiconductor substrate, in which or on which a plurality of circuit elements are formed. The circuit elements are electrically interconnected and, if necessary, connected to contact points, in particular to contact points disposed at an edge of the semiconductor substrate. The electrical interconnection is done with interconnect patterns which are provided in a plurality of contact-making planes, beginning with a first contact-making plane, which is closest to the main surface of the semiconductor substrate, and ranging to a last contact-making plane. The invention furthermore relates to a method for fabricating such a monolithically integrated semiconductor circuit apparatus.
Fuse structures are used in integrated circuits in order to interrupt ("fuse") or reestablish ("antifuse") electrically conductive connections through the use of laser irradiation after the actual production process. In programmable logic arrays (PLAs), the logic combinations are programmed by fuses. In safety-critical circuits, fuses are used to prevent access to test modes of the circuit by unauthorized persons. In the case of the use of fuses as in the method and the device of the invention, the fuses are used in order to activate redundant circuit sections, namely memory cells, and to disconnect defective ones. When using polysilicon fuses or else metal fuses for the redundancy activation of defective memory cells in dynamic random access memories (DRAMs) with many metalization layers, problems arise with regard to the reliability of the activation by burning through or "blowing" polysilicon interconnects or metal interconnects (M1 interconnects). These problems are further intensified, and have remained unsolved heretofore, when a semiconductor memory device normally having two metalization layers (M1, M2) and a digital logic component having, by contrast, at least one further metalization plane (M3) are intended to be combined on one and the same semiconductor substrate. Since the logic component thus has more than two metalization layers, severing polysilicon interconnects located at a deeper level for the purpose of activating the fuse is associated with great risks and faults.